Cypress FM4 Series - Page 779

CHAPTER 14: External Bus Interface
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 779
Figure 3-15 Chart Description for Automatic Wait Assignment
(NOR Flash Memory Page Read)
0 1 2 3 4 5 6 7 8 9
10
11 12 13 14 15
16
17 18 19
MAD[24:0]
MADATA[15:0]
MCSX[0]
First
read address cycle
Read
access
cycle 0
MOEX
Dat00 Dat02 Dat04 Dat06 Dat08 Dat10 Dat12
00 02 04 06 08 10 12 14
Read
access
cycle 1
Read
access
cycle 2
Read
access
cycle 3
Read
access
cycle 4
Read
access
cycle 5
Read
access
cycle 6
Read
access
cycle 7
FRADC=3
RACC=1 RACC=1 RACC=1 RACC=1
RACC=1 RACC=1
RACC=1
RACC=1
MCLK
(MCLKOUT)
Figure 3-16 Chart Description for Automatic Wait Assignment (SRAM Continuous Read)
DAT00
00 01 02 03
0
*
1 2 3 4 5 6 7 8 9
10
11 12 13 14 15
16
17 18 19
*
* *
MAD[24:0]
MADATA[7:0]
MOEX
MWEX
MDQM[0]
MCSX[0]
DAT01 DAT02 DAT03
RIDLC=1
RACC=3
RADC=2
RACC=3
RADC=2
RACC=3
RADC=2
RACC=3
RADC=2
MCLK
(MCLKOUT)
Figure 3-17 Chart Description of Automatic Wait Assignment (SDRAM)