Cypress FM4 Series - Page 778

CHAPTER 14: External Bus Interface
778 FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E
Figure 3-12 Chart Description for Automatic Wait Assignment (Separate Mode)
Figure 3-13 Chart Description for Automatic Wait Assignment (Multiplex Mode)
RD
Address
0 1 2 3 4 5 6 7 8 9
10
11 12
MADATA[15:0]
MOEX
MWEX
MDQM[0]
Read access cycle
MCSX
MALE
WD
Write access cycle
Address
Address
MAD[24:16]
Address
Address
MAD[15:0]
Address
13
ALC=2
ALES=1
ALEW=0
RACC=1
WACC=2
RADC=1
RIDLC=0
WIDLC=0
WWEC=0WADC=0
ALC=2
ALES=1
ALEW=1
MCLK
(MCLKOUT)
Figure 3-14 Chart Description for Automatic Wait Assignment (NAND Flash Memory Mode)
Status RD
0 1 2 3 4 5 6 7 8 9
10
11 12 13 14 15
16
17 18 19
MADATA[7:0]
MNREX
MNWEX
MCSX[0]
WADC=0
Read access cycle
WWEC
=0
MNCLE
MNALE
Busy
Busy
Read access cycle Read access cycle
Status read command
issuance
Ready
RADC=0
RIDLC=0
Status read Status read Status read
WACC=2 RACC=2
WIDLC=
0
RADC=0
RACC=2
RIDLC=0
RADC=0
RACC=2
RIDLC=0
R/B
(NAND Flash pin)
Write access cycle
RD
0 1 2 3 4 5 6 7 8 9 10 11 12
MADATA[15:0]
MOEX
MWEX
MDQM[0]
Read access cycle
MCSX
W D
Write access cycle
Address
MAD[24:16]
Address
Address
MAD[15:0]
Address
RACC=3 WACC=4
RADC=2
RIDLC=0
WIDLC=0
WWEC=0
WADC=2
MCLK
(MCLKOUT)
MCLK
(MCLKOUT)