CHAPTER 14: External Bus Interface
806 FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E
[bit5] PAGE (PAGE access mode): NOR Flash memory page access mode
This bit controls the mode of NOR Flash memory page access.
In NOR Flash memory page access mode, the first read access cycle (FRADC) setting can generate the
first address cycle. Subsequently, the read access cycle (RACC) setting can continue the access until it
reaches the 16-byte boundary.
To select NOR Flash memory page access mode, set the RBMON bit to 0 and the read access cycle
(RADC) to 0.
NOR Flash memory page access mode is turned OFF (Initial value)
NOR Flash memory page access mode is turned ON
[bit4] NAND: NAND Flash memory mode
This bit controls the mode used to connect with a NAND Flash memory.
To enable the access to a NAND Flash memory, set this bit to 1.
In NAND Flash memory mode, the corresponding MCSX is fixed to LOW and, subsequently, the pin
dedicated to the NAND Flash memory is used during the access. If this bit is set to 0 while the NAND
Flash memory is unused, then MCSX is fixed to HIGH, enabling the NAND Flash memory to maintain a
low power consumption state.
NAND Flash memory mode is turned OFF (Initial value)
NAND Flash memory mode is turned ON
[bit3] WEOFF (WEX OFF): Write Enable OFF
This bit can disable the write enable signal (MWEX) operation.
When the byte mask signal (MDQM) is used as a device write enable signal, disabling unnecessary
MWEX operation can reduce power consumption. When this bit is set to disable, MWEX is fixed to HIGH.
[bit2] RBMON: Read Byte Mask ON
This bit can enable the byte mask signal (MDQM) for read access.
The setting controls the output of unnecessary data from a device for which the byte mask signal is
enabled. This is helpful to reduce power consumption.
To Next Page
Loading...
