Cypress FM4 Series - Page 809

CHAPTER 14: External Bus Interface
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 809
 MPXCSOF bit: CS Assert Timing Setup
This bit is used to select MCSX assertion in multiplex mode from the start of accessing to the end of
address output complete (ALC period).
RD
Address
0 1 2 3 4 5 6 7 8 9
10
11 12
MADATA[31:0]
MOEX
MWEX
MDQM[0]
Read access cycle
MCSX
MALE
WD
Write access cycle
Address
Address
MAD[24:16]
Address
Address
MAD[15:0]
Address
13
ALC=2
ALES=1
ALEW=0
RACC=1
WACC=2
RADC=1
RIDLC=0
WIDLC=0
WWEC=0WADC=0
ALC=2
ALES=1
ALEW=1
In case of MPXCSOF=0
MCLKOUT
MCSX is asserted at the beginning of ALC period.
In case of MPXCSOF=1
RD
Address
0 1 2 3 4 5 6 7 8 9
10
11 12
MADATA[31:0]
MOEX
MWEX
MDQM[0]
Read access cycle
MCSX
MALE
WD
Write access cycle
Address
Address
MAD[24:16]
Address
Address
MAD[15:0]
Address
13
ALC=2
ALES=1
ALEW=0
RACC=1
WACC=2
RADC=1
RIDLC=0
WIDLC=0
WWEC=0WADC=0
ALC=2
ALES=1
ALEW=1
MCLKOUT
MCSX is asserted after the ALC period is completed.
Setting MPXCSOF=1 means that the MCSX assertion becomes the "address latch".
Therefore, it is enabled if address change is detected by change of MCSX.