Cypress FM4 Series - Page 810

CHAPTER 14: External Bus Interface
810 FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E
 SHRTDOUT bit: Write Data Retention Time in Idle Cycle
The WIDLC setup will extend the idle cycle.
The write data at that time will also be extended same as the specified period to become Hi-Z in the last
cycle.
0 1 2 3 4 5 6 7 8 9
MADATA[31:0]
MWEX
Write access cycle
MAD[24:16]
Address
MAD[15:0]
Address
MCSX
Address
WIDLC=0
Address
In case where WIDLC = 0 and SHRTDOUT = 0
MCLK
(MCLKOUT)
WD
The idle cycle is one cycle. The idle cycle will stop the data output to become Hi-Z.
0 1 2 3 4 5 6 7 8 9
MADATA[31:0]
MWEX
Write access cycle
MAD[24:16]
Address
MAD[15:0]
Address
MCSX
Add
WIDLC=2
Add
In case where WIDLC = 2 and SHRTDOUT = 0
MCLK
(MCLKOUT)
WD
Extended idle cycle makes the data Hi-Z at the last cycle.
In case where WIDLC = 2 and SHRTDOUT = 1
0 1 2 3 4 5 6 7 8 9
MADATA[31:0]
MWEX
Write access cycle
MAD[24:16]
Address
MAD[15:0]
Address
MCSX
Add
WIDLC=2
Add
MCLK
(MCLKOUT)
WD
Setting SHRTDOUT=1 extended the idle cycle but the data will become Hi-Z at the beginning of the idle
cycle.