Cypress FM4 Series - Page 822

CHAPTER 14: External Bus Interface
822 FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E
The following shows the table indicating the relationship between internal address bit and MAD bit at the
each setting of CASEL, RASEL, and, BASEL.
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Bit name Value
CASEL 00
0 1 2 3 4 5 6 7 8 9
01
0 1 2 3 4 5 6 7 8 9
RASEL 000
0 1 2 3 4 5 6 7 8 9 10 11 12 13
001
0 1 2 3 4 5 6 7 8 9 10 11 12 13
010
0 1 2 3 4 5 6 7 8 9 10 11 12 13
011
0 1 2 3 4 5 6 7 8 9 10 11 12 13
100
0 1 2 3 4 5 6 7 8 9 10 11 12 13
101
0 1 2 3 4 5 6 7 8 9 10 11 12 13
110
0 1 2 3 4 5 6 7 8 9 10 11 12 13
BASEL 000
14 15
001
14 15
010
14 15
011
14 15
100
14 15
101
14 15
110
14 15
Internal
address
[bit3] Reserved: Reserved bits
The read value is undefined.
Set this bit to 0 when writing.
[bit2]ROFF: Refresh OFF
This bit sets the refresh.
Use this bit to stop the refresh operation temporarily for the access to SDRAM command register etc. The
refresh counter itself is not stopped, but the refresh operation is not executed at the refresh timing. When
this bit is released, the refresh is implemented immediately if the refresh timing is passed. However, in
this time, only one refresh operation is executed even if two refresh timing is passed.
bit
Description
0
Refresh ON [Initial value]
1
Refresh OFF