CHAPTER 14: External Bus Interface
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 823
[bit1]PDON: Power Down ON
This bit set the power down mode.
For the detailed operations, see 3.9 Power Down Mode.
Power Down Mode OFF [Initial value]
[bit0] SDON: SDRAM ON
This bit enables the access to SDRAM.
In this operation, the power-on sequence is issued to SDRAM and the mode register setting etc. is
automatically made to enable the access to SDRAM.
When this bit is changed to 0 during the operation, the access to SDRAM is stopped thoroughly after
completing the access to SDRAM (if in refresh operation, after the refresh operation completion (after
(TREFC+1） (NREF+1) cycle). When PDON=1, MSDCKE is held at Low. During OFF, the data is not
saved because the refresh operation is not executed. For the access to SDRAM address area, the error
response is returned.
When SDRAM command register (SDCMD) is written in OFF state, the external bus interface does not
issue the power-on sequence and automatically sets this bit ON(=1) on the assumption that a user starts
SDRAM with a program. (in this case, set ROFF=1 (Refresh OFF).)
For the issued power-on sequence, see Figure 3-21.
Disables the access to SDRAM.[Initial value]
Enables the access to SDRAM.
Notes:
− The division ratio of SDRAM clock (MSDCLK) is set with MDIV bit of the division clock register
DCLKR).
− With beginning the clock supply by changing MSDCLKOFF from 1 to 0, do not change SDON
from 0 to 1 at the same time due to a delay in clock output.
− When the refresh is aborted temporarily wit ROFF, to hold the data, note that the temporary abort
time does not exceed the refresh timing or execute the refresh explicitly by accessing SDRAM
command register (SDCMD)
− Change SDON to 1 after completing the setting of REFTIM, PWRDWN, and SDTIM registers
except SDMODE.SDON.
− Because SDON bit control is performed on the AHB side, set SDON to ON (=1) from the APB
interface, check that the readout value of this bit has become 1, and then access the SDRAM.
Address Area
− External bus interface has 1792 MB SDRAM address area.
− The maximum size of address output to the outside by the setting of BASEL, RASEL, and CASEL
is 128 MB.
− For the address area on the memory map, see Figure 6-1.
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