NXP Semiconductors KL25 Series - Page 11

Section number Title Page
14.3 Low-voltage detect (LVD) system................................................................................................................................237
14.3.1 LVD reset operation.....................................................................................................................................238
14.3.2 LVD interrupt operation...............................................................................................................................238
14.3.3 Low-voltage warning (LVW) interrupt operation.......................................................................................238
14.4 I/O retention..................................................................................................................................................................239
14.5 Memory map and register descriptions.........................................................................................................................239
14.5.1 Low Voltage Detect Status And Control 1 register (PMC_LVDSC1)........................................................240
14.5.2 Low Voltage Detect Status And Control 2 register (PMC_LVDSC2)........................................................241
14.5.3 Regulator Status And Control register (PMC_REGSC)..............................................................................242
Chapter 15
Low-Leakage Wakeup Unit (LLWU)
15.1 Introduction...................................................................................................................................................................245
15.1.1 Features........................................................................................................................................................245
15.1.2 Modes of operation......................................................................................................................................246
15.1.3 Block diagram..............................................................................................................................................247
15.2 LLWU signal descriptions............................................................................................................................................248
15.3 Memory map/register definition...................................................................................................................................248
15.3.1 LLWU Pin Enable 1 register (LLWU_PE1)................................................................................................249
15.3.2 LLWU Pin Enable 2 register (LLWU_PE2)................................................................................................250
15.3.3 LLWU Pin Enable 3 register (LLWU_PE3)................................................................................................251
15.3.4 LLWU Pin Enable 4 register (LLWU_PE4)................................................................................................252
15.3.5 LLWU Module Enable register (LLWU_ME)............................................................................................253
15.3.6 LLWU Flag 1 register (LLWU_F1).............................................................................................................255
15.3.7 LLWU Flag 2 register (LLWU_F2).............................................................................................................257
15.3.8 LLWU Flag 3 register (LLWU_F3).............................................................................................................258
15.3.9 LLWU Pin Filter 1 register (LLWU_FILT1)..............................................................................................260
15.3.10 LLWU Pin Filter 2 register (LLWU_FILT2)..............................................................................................261
15.4 Functional description...................................................................................................................................................262
15.4.1 LLS mode.....................................................................................................................................................263
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
Freescale Semiconductor, Inc. 11