Section number Title Page
18.2.3 Platform Control Register (MCM_PLACR)................................................................................................293
18.2.4 Compute Operation Control Register (MCM_CPO)...................................................................................296
Chapter 19
Micro Trace Buffer (MTB)
19.1 Introduction...................................................................................................................................................................299
19.1.1 Overview......................................................................................................................................................299
19.1.2 Features........................................................................................................................................................302
19.1.3 Modes of Operation.....................................................................................................................................303
19.2 External Signal Description..........................................................................................................................................303
19.3 Memory Map and Register Definition..........................................................................................................................304
19.3.1 MTB_RAM Memory Map...........................................................................................................................304
19.3.2 MTB_DWT Memory Map...........................................................................................................................316
19.3.3 System ROM Memory Map.........................................................................................................................326
Chapter 20
Crossbar Switch Lite (AXBS-Lite)
20.1 Introduction...................................................................................................................................................................331
20.1.1 Features........................................................................................................................................................331
20.2 Memory Map / Register Definition...............................................................................................................................331
20.3 Functional Description..................................................................................................................................................332
20.3.1 General operation.........................................................................................................................................332
20.3.2 Arbitration....................................................................................................................................................333
20.4 Initialization/application information...........................................................................................................................334
Chapter 21
Peripheral Bridge (AIPS-Lite)
21.1 Introduction...................................................................................................................................................................335
21.1.1 Features........................................................................................................................................................335
21.1.2 General operation.........................................................................................................................................335
21.2 Functional description...................................................................................................................................................336
21.2.1 Access support.............................................................................................................................................336
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
Freescale Semiconductor, Inc. 13