1. A system reset is held on internal logic, the RESET pin is driven out low, and the
MCG is enabled in its default clocking mode.
2. Required clocks are enabled (System Clock, Flash Clock, and any Bus Clocks that do
not have clock gate control reset to disabled).
3. The system reset on internal logic continues to be held, but the Flash Controller is
released from reset and begins initialization operation while the Reset Control logic
continues to drive the RESET pin out low.
4. Early in reset sequencing the NVM option byte is read and stored to FTFA_FOPT. If
the bits associated with LPBOOT are programmed for an alternate clock divider reset
value, the system/core clock is switched to a slower clock speed. If the FAST_INIT
bit is programmed clear, the Flash initialization switches to slower clock resulting
longer recovery times.
5. When Flash Initialization completes, the RESET pin is released. If RESET continues
to be asserted (an indication of a slow rise time on the RESET pin or external drive
in low), the system continues to be held in reset. Once the RESET pin is detected
high, the Core clock is enabled and the system is released from reset.
6. When the system exits reset, the processor sets up the stack, program counter (PC),
and link register (LR). The processor reads the start SP (SP_main) from vector-table
offset 0. The core reads the start PC from vector-table offset 4. LR is set to
0xFFFF_FFFF. The CPU begins execution at the PC location.
Subsequent system resets follow this same reset flow.
Boot
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
136 Freescale Semiconductor, Inc.
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