NXP Semiconductors KL25 Series - Page 172

Table 10-16. SPI0 Signal Descriptions
Chip signal name Module signal
name
Description I/O
SPI0_MISO MISO Master Data In, Slave Data Out I/O
SPI0_MOSI MOSI Master Data Out, Slave Data In I/O
SPI0_SCLK SPSCK SPI Serial Clock I/O
SPI0_PCS0 SS Slave Select I/O
Table 10-17. SPI1 Signal Descriptions
Chip signal name Module signal
name
Description I/O
SPI1_MISO MISO Master Data In, Slave Data Out I/O
SPI1_MOSI MOSI Master Data Out, Slave Data In I/O
SPI1_SCLK SPSCK SPI Serial Clock I/O
SPI1_PCS0 SS Slave Select I/O
Table 10-18. I
2
C 0 Signal Descriptions
Chip signal name Module signal
name
Description I/O
I2C0_SCL SCL Bidirectional serial clock line of the I
2
C system. I/O
I2C0_SDA SDA Bidirectional serial data line of the I
2
C system. I/O
Table 10-19. I
2
C 1 Signal Descriptions
Chip signal name Module signal
name
Description I/O
I2C1_SCL SCL Bidirectional serial clock line of the I
2
C system. I/O
I2C1_SDA SDA Bidirectional serial data line of the I
2
C system. I/O
Table 10-20. UART 0 Signal Descriptions
Chip signal name Module signal
name
Description I/O
UART0_TX TXD Transmit data O
UART0_RX RXD Receive data I
Module Signal Description Tables
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
172 Freescale Semiconductor, Inc.