Table 17-2. Cycle definitions of decorated store: logical OR
Pipeline Stage Cycle
x x+1 x+2
BME AHB_ap Forward addr to memory;
Decode decoration; Convert
master_wt to slave_rd;
Capture address, attributes
Recirculate captured addr +
attr to memory as slave_wt
<next>
BME AHB_dp
<previous>
Perform memory read; Form
(rdata | wdata) and capture
destination data in register
Perform write sending
registered data to memory
17.4.1.3 Decorated Store: Logical XOR (XOR)
This command performs an atomic read-modify-write of the referenced memory location.
First, the location is read; it is then modified by performing a logical XOR (exclusive-
OR) operation using the write data operand sourced for the system bus cycle; finally, the
result of the XOR operation is written back into the referenced memory location.
The data size is specified by the write operation and can be byte (8-bit), halfword (16-bit)
or word (32-bit). The core performs the required write data lane replication on byte and
halfword transfers.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ioxorb 0 1 0 0 1 1 - - - - - - mem_addr
ioxorh
0 1 0 0 1 1 - - - - - - mem_addr 0
ioxorw
0 1 0 0 1 1 - - - - - - mem_addr 0 0
Figure 17-5. Decorated Address Store: Logical XOR
where addr[28:26] = 011 specifies the XOR operation, and mem_addr[19:0] specifies the
address offset into the peripheral space based at 0x4000_0000. The "-" indicates an
address bit "don't care".
The decorated XOR write operation is defined in the following pseudo-code as:
ioxor<sz>(accessAddress, wdata) // decorated store XOR
tmp = mem[accessAddress & 0xE00FFFFF, size] // memory read
tmp = tmp ^ wdata // modify
mem[accessAddress & 0xE00FFFFF, size] = tmp // memory write
The cycle-by-cycle BME operations are detailed in the following table.
Functional Description
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
278 Freescale Semiconductor, Inc.
To Next Page
Loading...
