• Cycle x, 1st AHB address phase: Read from input bus is translated into a read
operation on the output bus with the actual memory address (with the decoration
removed) and then captured in a register
• Cycle x+1, 2nd AHB address phase: Write access with the registered (but actual)
memory address is output
• Cycle x+1, 1st AHB data phase: The "original" 1-bit memory read data is captured in
a register, while the 1-bit field is set or clear based on the function defined by the
decoration with the modified data captured in a register; the input bus cycle is stalled
• Cycle x+2, 2nd AHB data phase: The selected original 1-bit is right justified, zero
filled and then driven onto the input read data bus, while the registered write data is
sourced onto the output write data bus
NOTE
Any wait states inserted by the peripheral slave device
(sx_hready = 0) are simply passed through the BME back to the
master input bus, stalling the AHB transaction cycle for cycle.
A generic timing diagram of a decorated load showing an unsigned bit field operation is
shown in the following figure.
Functional Description
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
282 Freescale Semiconductor, Inc.
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