NXP Semiconductors KL25 Series - Page 85

Signal multiplexing
Module signals
Register
access
TPM
Peripheral bus
controller 0
Other peripherals
Figure 3-24. TPM configuration
Table 3-36. Reference links to related information
Topic Related module Reference
Full description Timer/PWM Module Timer/PWM Module
System memory map System memory map
Clocking Clock distribution
Power management Power management
Signal multiplexing Port control Signal multiplexing
3.8.1.1 TPM Instantiation Information
This device contains three Low Power TPM modules (TPM). All TPM modules in the
device only are configured as basic TPM function, and no quadrature decoder function
and all can be functional in Stop/VLPS mode. The clock source is either external or
internal in Stop/VLPS mode.
The following table shows how these modules are configured.
Table 3-37. TPM configuration
TPM instance Number of channels Features/usage
TPM0 6 Basic TPM,functional in Stop/VLPS mode
TPM1 2 Basic TPM,functional in Stop/VLPS mode
TPM2 2 Basic TPM,functional in Stop/VLPS mode
There are several connections to and from the TPMs in order to facilitate customer use
cases. For complete details on the TPM module interconnects please refer to the Module-
to-Module section.
Chapter 3 Chip Configuration
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
Freescale Semiconductor, Inc. 85