NXP Semiconductors KL25 Series - Page 9

Section number Title Page
11.2.2 Modes of operation......................................................................................................................................176
11.3 External signal description............................................................................................................................................176
11.4 Detailed signal description............................................................................................................................................177
11.5 Memory map and register definition.............................................................................................................................177
11.5.1 Pin Control Register n (PORTx_PCRn).......................................................................................................183
11.5.2 Global Pin Control Low Register (PORTx_GPCLR)..................................................................................185
11.5.3 Global Pin Control High Register (PORTx_GPCHR).................................................................................186
11.5.4 Interrupt Status Flag Register (PORTx_ISFR)............................................................................................186
11.6 Functional description...................................................................................................................................................187
11.6.1 Pin control....................................................................................................................................................187
11.6.2 Global pin control........................................................................................................................................188
11.6.3 External interrupts........................................................................................................................................188
Chapter 12
System integration module (SIM)
12.1 Introduction...................................................................................................................................................................191
12.1.1 Features........................................................................................................................................................191
12.2 Memory map and register definition.............................................................................................................................191
12.2.1 System Options Register 1 (SIM_SOPT1)..................................................................................................193
12.2.2 SOPT1 Configuration Register (SIM_SOPT1CFG)....................................................................................194
12.2.3 System Options Register 2 (SIM_SOPT2)..................................................................................................195
12.2.4 System Options Register 4 (SIM_SOPT4)..................................................................................................197
12.2.5 System Options Register 5 (SIM_SOPT5)..................................................................................................199
12.2.6 System Options Register 7 (SIM_SOPT7)..................................................................................................200
12.2.7 System Device Identification Register (SIM_SDID)...................................................................................202
12.2.8 System Clock Gating Control Register 4 (SIM_SCGC4)............................................................................204
12.2.9 System Clock Gating Control Register 5 (SIM_SCGC5)............................................................................206
12.2.10 System Clock Gating Control Register 6 (SIM_SCGC6)............................................................................207
12.2.11 System Clock Gating Control Register 7 (SIM_SCGC7)............................................................................209
12.2.12 System Clock Divider Register 1 (SIM_CLKDIV1)...................................................................................210
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
Freescale Semiconductor, Inc. 9