Xilinx virtex-5 fpga User Manual

384 www.xilinx.com Virtex-5 FPGA User Guide
UG190 (v5.0) June 19, 2009
class II (1.8V) 265
class III 259
class III (1.8V) 270
class IV 260
class IV (1.8V) 271
CSE differential HSTL class II 265
Differential HSTL class II 264, 267
differential HSTL class II 256
HyperTransport
HT
296
I
I/O standards 218
bank rules 298
compatibility 299
differential I/O 218
single-ended I/O 218
I/O tile 217
ILOGIC 217
IOB 217
OLOGIC 217
IBUF 233
PULLUP/PULLDOWN/KEEPER
237
IBUFDS 234
IBUFDS_DIFF_OUT 235
IBUFG 26, 233
IBUFGDS 26, 234
IDDR 319
OPPOSITE_EDGE mode 319
ports 321
primitive 321
SAME_EDGE mode 320
SAME_EDGE_PIPELINED mode
320
IDELAY 325
defined 325
attributes 329
delay mode
fixed
325
variable 325
zero-hold time 325
IDELAYCTRL 337
increment/decrement 328
primitive 326
switching characteristics 330
timing 330
IDELAYCTRL 337
instantiating 340, 342
RDY port 341
location 339
primitive 338
REFCLK 337, 343
ILOGIC 217, 318
IDDR 319
SR 318
switching characteristics 324
timing 322
IOB 217
defined 218
IOBUF 234
PULLUP/PULLDOWN/KEEPER
237
IOBUFDS 236
IODELAY 325
DATAIN 327
DATAOUT 327
IDATAIN 327
ODATAIN 327
ports 327
ISERDES 353
defined 353
attributes 358
bitslip 353, 356, 367
BITSLIP_ENABLE attribute
358
IDELAY
IDELAYCTRL
337
ports 355, 372
primitive 354
serial-to-parallel converter 353, 362
switching characteristics 363
timing models 363
width expansion 361
L
LDT
See HyperTransport
296
LVCMOS 241
defined 241
LVDCI 243
defined 243
LVDCI_DV2 244
source termination 303
LVDS 294
defined 294
LVDS_25_DCI 295
LVPECL 297
defined 297
LVTTL 239
defined 239
M
multirate
FIFO
115, 139
N
NO_CHANGE mode 118
O
OBUF 233
OBUFDS 235
OBUFT 234
PULLUP/PULLDOWN/KEEPER
237
OBUFTDS 235
ODDR 345
clock forwarding 347
OPPOSITE_EDGE mode 346
ports 347
primitive 347
SAME_EDGE mode 346
OLOGIC 217, 344
timing 348
OSERDES 370
parallel-to-serial converter 370
switching characteristics 377
timing 377, 378
P
parallel-to-serial converter 370
DDR 370
SDR 370
PCI 247
PFDM 312
PLL
allocation in device
48
PSCLK 52
R
READ_FIRST mode 118
REFCLK 338, 343
regional clock buffers 25, 40
regional clocks
clock buffers
42
clock nets 46
REV 318
RSDS 296

Xilinx virtex-5 fpga Specifications

General

Brand	Xilinx
Model	virtex-5 fpga
Category	Computer Hardware
Language	English