Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.0) June 19, 2009
02/02/07 3.0 Added the three SXT devices and the XC5VLX220T to Table 1-5, Table 2-1, and Table 5-2.
Chapter 4: Clarified wording in “Synchronous Clocking” on page 119.
Chapter 6: Added “DCI Cascading” on page 220. Changed V
REF
for SSTL18_II_T_DCI to
0.9 in Table 6-39.
Chapter 7: Revised OQ in Figure 7-27, page 349.
Chapter 8: “Clock Enable Inputs - CE1 and CE2” on page 356.
09/11/07 3.1 Chapter 1: Added “Clock Gating for Power Savings” on page 26. Revised Figure 1-2,
page 30. Revised Figure 1-16, page 37.
Chapter 2: Revised DCM reset and locking process in “Reset Input - RST,” page 53.
Updated DO[2] description in Table 2-4, page 56. Changed the multiply value range on
page 58. Revised the description for “FACTORY_JF Attribute,” page 61. Revised
“Output Clocks,” page 65, updated Figure 2-7, page 74, and added a BUFG to Figure 2-
10, page 72. Added more steps to Dynamic Reconfiguration (DRPs) when loading new
M and D values on page 73. Updated Figure 2-7, page 74. Revised bulleted descriptions
under Figure 2-20, page 87.
Chapter 3: Updated Figure 3-1, page 90. Add notes to Table 3-2, page 93. Added a note
to “Phase Shift,” page 95. Added rounding to Equation 3-3 through Equation 3-6.
Revised CLKFBIN, CLKFBDCM, CLKFBOUT, RST, LOCKED, and added the REL pin
and note 2 to Table 3-3, page 96. Added RESET_ON_LOSS_OF_LOCK attribute to
Table 3-4, page 98. Removed general routing discussion from “PLL Clock Input
Signals.”Revised “Missing Input Clock or Feedback Clock” section. Added waveforms
to Figure 3-13. Corrected the Virtex-4 port mapping in Figure 3-17 and Table 3-8,
page 111.
Chapter 4: Revised and clarified “Built-in Error Correction.” Edited WE signal
throughout. Clarified Readback limitation in “Simple Dual-Port Block RAM” on
page 121. Edited “Set/Reset - SSR[A|B],” page 125. Added “Block RAM Retargeting,”
page 139. Revised latency values and added Note 1 to Table 4-16, page 145. Updated
“Cascading FIFOs to Increase Depth,” page 157.
Chapter 5: Clarified information about common control signals in a slice in “Storage
Elements” on page 178.
Chapter 6: Updated the DCI cascading guidelines on page 223. Removed references to
“HSLVDCI Controlled Impedance Driver with Unidirectional Termination” since it is
not supported in software. Added note 3 to Table 6-17, page 256. Clarified the
introduction to “SSTL (Stub-Series Terminated Logic),” page 274. Revised
“DIFF_SSTL2_II_DCI, DIFF_SSTL18_II_DCI” on page 275. Fixed DIFF_SSTL2_II
references in Figure 6-74, page 282. Revised rules 2 and 3 in “Rules for Combining I/O
Standards in the Same Bank,” page 298. Deleted of absolute maximum table from
“Overshoot/Undershoot,” page 302.
Chapter 7: Removed DDLY port from IDDR primitive page 321. Added the SIGNAL
_PATTERN, DELAY_SRC, and REFCLK_FREQUENCY attributes to Table 7-10,
page 329. Revised Figure 7-9, page 330. Removed Table 7-12: “Generating Reference
Clock From DCM” and updated REFCLK section in “IDELAYCTRL Ports” on page 338.
Clarified introduction in “IDELAYCTRL Locations,” page 339. Changed ODDR “Clock
Forwarding,” page 347.
Chapter 8: Updated SR and O in Figure 8-2 and Table 8-1, page 355. Updated the entire
section for “BITSLIP Submodule,” page 366. Fixed typographical errors in Figure 8-14,
page 370.
Date Version Revision
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