Cypress FM4 Series - Page 255

CHAPTER 7-2: VBAT Domain(A)
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 255
 PWRITE/PREAD
Performs a bulk save/recall operation for the registers shown in Table 2-7, which are included in the VBAT
port circuit.
Table 2-7 List of Registers Transferred by PWRITE/PREAD
No.
Register Name
Reference
No.
Register Name
Reference
1
WTCAL0
[RTCCLK]
2
WTCAL1
[RTCCLK]
3
WTCALEN
[RTCCLK]
4
WTDIV
[RTCCLK]
5
WTDIVEN
[RTCCLK]
6
WTCALPRD
[RTCCLK]
7
WTCOSEL
[RTCCLK]
8
CCS
2.3 32 kHz Oscillation Circuit
9
CCB
2.3 32 kHz Oscillation Circuit
10
Reserved
-
11
BOOST
2.3 32 kHz Oscillation Circuit
12
WTOSCCNT
2.3 32 kHz Oscillation Circuit
13
VBPFR
2.6 VBAT I/O Ports
14
VBPCR
2.6 VBAT I/O Ports
15
VBDDR
2.6 VBAT I/O Ports
16
VBPZR
2.6 VBAT I/O Ports
17
VBDOR
2.6 VBAT I/O Ports
For the function of each register, see [RTCCLK], which stands for Chapter RTC Clock Control Block in
Timer Part, and "2.6 VBAT I/O Ports" and "2.3 32 kHz Oscillation Circuit" in this chapter.
The interface circuit type for registers No.1 to No.17 of the VBAT port circuit is type 3.
A save operation is started if 1 is written to bit5 in the WTCR20 Register. This save operation is called a
PWRITE operation.
A recall operation is started if 1 is written to bit4 in the WTCR20 Register. This recall operation is called a
PREAD operation.
The transfer clock is created by dividing PCLK2 by the value of the VB_CLKDIV Register.
The RTC transfers 1 byte of data for one transfer clock.
In one PREAD/PWRITE operation, the RTC transfers data of registers in sequence from No.1 to No.17
shown in Table 2-7.
Since the registers of the VBAT port circuit are 17 bytes in size, the data transfer ends as 17 transfer
clocks elapse.