Cypress FM4 Series - Page 763

CHAPTER 14: External Bus Interface
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 763
 Multiplex Mode
This mode inputs/outputs the address/data to MADATA[15:0] pins in a time division manner. As the part of
address pins and data pins are shared, fewer pins are used for accessing the external memories. An
example of waveform in multiplex mode is shown in Figure 3-2.
Figure 3-2 Example of Waveform in Multiplex Mode
RD
Address
0 1 2 3 4 5 6 7 8 9
10
11 12
MADATA[31:0]
MOEX
MWEX
MDQM[0]
Read access cycle
MCSX
MALE
WD
Write access cycle
Address
Address
MAD[24:16]
Address
Address
MAD[15:0]
Address
MCLK
(MCLKOUT)
Summary of selected bus access mode and their pin functions is shown in Table 3-1.
Table 3-1 Bus Access Mode and Pin Function
Pin
32-bit
Separate
32-bit
Multiplex
16-bit
Separate
16-bit
Multiplex
8-bit
Separate
8-bit
Multiplex
MAD[24:16]
Address [24:16]
(Address [24:16])
Address [24:16]
Address [24:16]
Address [24:16]
Address [24:16]
MAD[15:8]
Address [15:8]
(Address [15:8])
Address [15:8]
(Address [15:8])
Address [15:8]
(Address [15:8])
MAD[7:0]
Address [7:0]
(Address [7:0])
Address [7:0]
(Address [7:0])
Address [7:0]
(Address [7:0])
MADATA[31:25]
Data [31:25]
Data [31:25]
Output none
Output none
Output none
Output none
MADATA[24:16]
Data [24:16]
Address [24:16]
Data [25:16]
Multiplex
Output none
Output none
Output none
Output none
MADATA[15:8]
Data [15:8]
Address [15:8]
Data [15:8]
Multiplex
Data [15:8]
Address [15:8]
Data [15:8]
Multiplex
No output
(Address [15:8])
MADATA[7:0]
Data [7:0]
Address [7:0]
Data [7:0]
Multiplex
Data [7:0]
Address [7:0]
Data [7:0]
Multiplex
Data [7:0]
Address [7:0]
Data [7:0]
Multiplex
Notes:
− Address output from MAD pins in multiplex mode is available depending on the GPIO setups.
− Placement of the external bus interface pins depends on the product type. See the data sheets of
products used for the details.