Keithley 4200A-SCS

In this appendix:
Introduction ............................................................................... L-1
JEDEC standards ..................................................................... L-2
HCI and WLR projects .............................................................. L-2
HCI degradation: Background information ................................ L-9
Configuration sequence for subsite cycling .............................. L-9
V-ramp and J-ramp tests ........................................................ L-10
Introduction
This section provides information on wafer-level reliability (WLR) testing. Included are tests for:
• Hot-carrier injection (HCI)
• Negative-bias temperature instability (NBTI)
• Electromigration
• Charge-to-breakdown measurement (QBD)
AC, or pulsed, stress is a useful addition to the typical stress-measure tests for investigating both
semiconductor charge trapping and degradation behaviors. NBTI and time-dependent dielectric
breakdown (TDDB) tests consist of stress / measure cycles.
The applied stress voltage is a DC signal, which is used because it maps more easily to device
models. Incorporating pulsed stress testing provides additional data that permits a better
understanding of device performance in frequency-dependent circuits.
The test pulse stresses the device for HCI, NBTI, and TDDB test instead of DC bias by outputting a
train of pulses for a period of time (stress time). Pulse characteristics are not changed during the
stress-measure test. The test then uses SMUs to measure device characteristics such as V
th
and G
m
.
This section includes background information on HCI degradation and summaries for using 4200A-
SCS projects to measure HCI degradation and other WLR tests.
The projects for HCI and QBD testing comply with the standard procedures established by JEDEC.
In 4200A-SCS documentation, all references to the JEDEC standards and duplicated JEDEC
documentation are clearly indicated as JEDEC copyright-protected material.
Appendix L
Wafer-level reliability testing