D: Using a Model 82 C-V System Model 4200A-SCS Parameter Analyzer
D-12 4200A-901-01 Rev. C / February 2017
5. Select Run to execute the test.
6. Follow the instructions on the dialog boxes, which will guide you through the cable compensation
process. The three basic dialog boxes are shown below.
 Measure offset: An open circuit measurement is required. Open the circuit as close to the
DUT as possible.
 Measure capacitance source: Connect a capacitance source in place of the DUT. Note that
the value in the dialog box corresponds to a calibration value you entered in
Enter and save
capacitance source values (on page D-10). Connect the capacitance source as close to the
DUT as possible.
 Compare readings: Compares the measured value to the calibration (nominal) value you
entered. The two readings should be fairly close. If they are not, the wrong capacitance
source may have been connected or an open circuit condition occurred. In that case, click
Cancel to abort the cable compensation process.
Figure 589: Cable compensation dialog boxes
Clicking Cancel in a cable compensation dialog box aborts the cable compensation process. To start
over, click Run.
Capacitance tests
The following topics describe the user modules that can be made into tests Clarius.
QTsweep (equilibrium test)
To achieve accurate simultaneous C-V test results, measurements must be made with the device in
equilibrium. A device is considered to be in equilibrium when all internal capacitances are fully
charged before measuring the capacitance. For a fully charged capacitor, any measured current is
leakage.
After voltage step is applied to the device, a delay time is used to allow capacitances to fully charge
before measuring quasistatic capacitance. If the delay time is too short (capacitors still charging), the
quasistatic capacitance measurement will not be accurate. This test allows you to determine the
delay time required to achieve equilibrium.
This example assumes that the Model 82 is connected directly to the DUT. The DUT could be a
device installed in a test fixture, or a substrate on a wafer.
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