L: Wafer-level reliability testing Model 4200A-SCS Parameter Analyzer
L-2 4200A-901-01 Rev. C / February 2017
JEDEC standards
The following descriptions for the JESD28-A and JESD35-A standard procedures have been
acquired from the JEDEC website. This is JEDEC copyright-protected material.
JESD28-A
Published: Dec-2001
A Procedure for Measuring N-Channel MOSFET Hot-Carrier-Induced Degradation Under DC
Stress
This document describes an accelerated test for measuring the hot-carrier-induced degradation of a
single n-channel MOSFET using DC bias. The purpose of this document is to specify a minimum set
of measurements so that valid comparisons can be made between different technologies, IC
processes, and process variations in a simple, consistent, and controlled way. The measurements
specified should be viewed as a starting point in the characterization and benchmarking of the
transistor manufacturing process.
JESD35-A
Published: Apr-2001
Procedure for Wafer-Level Testing of Thin Dielectrics
This document is intended for use in the MOS Integrated Circuit manufacturing industry fabrication
processing and test and describes procedures developed for estimating the overall integrity and
reliability of thin gate oxides. Three basic test procedures are described: the voltage-ramp (V-Ramp),
the current-ramp (J-Ramp), the current-ramp (J-Ramp), and the constant current (Bounded J-Ramp)
test. Each test is designed for simplicity, speed, and ease of use.
The JEDEC standard procedures are available on the JEDEC website (http://www.jedec.org).
When you visit the JEDEC website, you must register before you can access the standards.
Registration is free.
HCI and WLR projects
The 4200A-SCS projects for HCI and WLR testing include:
• hci-1-dut
• hci-4-dut
• nbti-1-dut
• em-const-i
• qbd
All of these projects except qbd use subsite cycling in the stress/measure mode. For details, see
Subsite cycling (on page 6-181
).
You can use each of these projects as configured or modify them for your testing requirements.
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