Mips Technologies R4000 - System Control Coprocessor

Chapter 4
80 MIPS R4000 Microprocessor User's Manual
4.3 System Control Coprocessor
The System Control Coprocessor (CP0) is implemented as an integral part
of the CPU, and supports memory management, address translation,
exception handling, and other privileged operations. CP0 contains the
registers shown in Figure 4-7 plus a 48-entry TLB. The sections that follow
describe how the processor uses the memory management-related
registers
†
.
Each CP0 register has a unique number that identifies it; this number is
referred to as the register number. For instance, the Page Mask register is
register number 5.
Figure 4-7 CP0 Registers and the TLB
† For a description of CP0 data dependencies and hazards, please see Appendix F.
EntryLo0
2*
EntryHi
Page Mask
Index
Random
Wired
Count
47
0
BadVAddr
TLB
(“Safe” entries)
(See Random Register,
PRId
0127
8*
15*
Compare
11*
Config
16*
LLAddr
17*
WatchLo
18*
WatchHi
19*
TagLo
28*
TagHi
29*
contents of TLB Wired)
ECC
26*
*Register number
Used with exception
processing. See
Used with memory
Chapter 5 for details.
EntryLo0
2*
3*
EntryLo1
EntryHi
10*
5*
Page Mask
Index
0*
Random
1*
Wired
6*
ErrorEPC
30*
Context
4*
Status
12*
Cause
13*
EPC
14*
management system.
CacheErr
27*
XContext
20*
9*