Chapter 12
326 MIPS R4000 Microprocessor User's Manual
Store Hit
This section describes store hits in both secondary-cache and no-
secondary-cache mode.
Secondary-Cache Mode
When the processor hits in the secondary cache, on a line that is marked
either shared or dirty shared, the processor must issue an update or
invalidate request and then wait to receive an acknowledge, before the
store is complete. The processor checks the coherency attribute in the TLB
for the page containing the cache line that is target of the store, to
determine if the cache line is managed by either a write invalidate or write
update cache coherency protocol.
• If the coherency attribute is sharable or exclusive, a write
invalidate protocol is in effect, and the processor issues an
invalidate request. The processor cannot complete the store
until the external agent signals an acknowledge for this
invalidate request.
• If the coherency attribute is update, a write update protocol is
in effect, and the processor issues an update request. The
processor cannot complete the store until the external agent
signals an acknowledge for this update request.
No-Secondary-Cache Mode
In no-secondary-cache mode, all lines are set to the dirty exclusive state.
This means store hits cause no bus transactions.
Uncached Loads or Stores
When the processor performs an uncached load, it issues a noncoherent
doubleword, partial doubleword, word, or partial word read request.
When the processor performs an uncached store, it issues a doubleword,
partial doubleword, word, or partial word write request.
External requests have a higher priority than uncached stores. When
using the uncached store buffer on an R4400 processor, it is possible for the
external agent to receive cached and uncached stores out of program
order, as the example below illustrates. Figure 12-14 shows a cached and
uncached store instruction sequence:
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