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Mips Technologies R4000 - No-Secondary-Cache Mode

Mips Technologies R4000
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MIPS R4000 Microprocessor User's Manual 325
System Interface
Nullifying a Potential Update: If the processor issues a cluster that
contains a potential update, and the response data for the read request
is returned in either a clean exclusive or dirty exclusive state, the
potential update is nullified. Once a potential update has been
nullified, the external agent must discard the update. The processor
does not wait for or expect an acknowledge to a potential update that
has been nullified. It is not correct to assert either IvdAck* or IvdErr*
in this situation.
If the read response data is returned in either the clean exclusive or dirty
exclusive state, the processor cannot issue an update request. It is
assumed that the external agent will take the appropriate action to change
the state of the cache line to invalid in other caches.
An external request indicating processor update cancellation can be issued
when a processor read is not pending or when compulsory update is
unacknowledged. Processor state is undefined if a cancellation is signaled
on an external coherence request to the processor when a processor read
is pending, or there is no unacknowledged compulsory update.
No-Secondary-Cache Mode
The processor issues a read request for the cache line that contains the data
element to be loaded, then awaits the external agent to provide read data
in response to the read request. Then, if the current cache line must be
written back, the processor issues a write request for the current cache line.
In no-secondary-cache mode, if the new cache line replaces a current cache
line whose Write back (W) bit is set, the current cache line moves to an
internal write buffer before the new cache line is loaded in the primary
cache.

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