Mips Technologies R4000 - External Null Request Protocol

Chapter 12
344 MIPS R4000 Microprocessor User's Manual
Figure 12-29 External Read Request, System Interface in Master State
NOTE: The processor does not contain any resources that are
readable by an external read request; in response to an external read
request the processor returns undefined data and a data identifier
with its Erroneous Data bit, SysCmd(5), set.
External Null Request Protocol
The processor supports two kinds of external null requests.
•Asecondary cache release external null request returns ownership
of the secondary cache to the processor while the System
interface remains in slave state, until another external null
request returns it to master state.
•ASystem interface release external null request returns the System
interface to master state from slave state without otherwise
affecting the processor.
SCycle
1 2 3 4 5 6 7 8 9 10 11 12
SClock
SysAD Bus
Addr Data0
SysCmd Bus
Read NEOD
ValidOut*
ValidIn*
ExtRqst*
Release*
6
1
2
3
5
6
4
Master
Slave
Master