Chapter 11
280 MIPS R4000 Microprocessor User's Manual
Handling Coherency Conflicts
Coherency conflicts are examined and resolved based on the current state
of the processor. Referring to Figure 11-12, the following conflicts and
their resolutions are described in this section:
• coherent read conflicts
• coherent write conflicts
• invalidate conflicts
Coherent Read Conflicts
External coherency requests that conflict with pending processor coherent
read requests can be issued to the processor without affecting processor
behavior. In the system model shown in Figure 11-12, no conflict
detection is performed by the external agent for processor coherent read
requests; if an external intervention request or invalidate request is
forwarded to the processor that is in conflict with a pending processor
coherent read request, it does not affect the processor cache since the
targeted cache line is, by definition, absent from the cache. The processor
effectively discards the conflicting external intervention request,
responding with an invalid indication for the targeted cache line.
Similarly, the processor discards a conflicting external invalidate request
since the targeted cache line is not present and therefore invalid.
For pending processor coherent read requests, conflict detection could be
added to a system similar to the one shown in Figure 11-12. In such a case,
when the external agent sees a read response on the bus that conflicts with
a pending processor coherent read request, the external agent does not
issue an intervention request to the processor. Rather, it simply reacts as
if an intervention request has been completed and the cache line is not
present in the processor cache.
Similarly, when an external agent sees an invalidate request on the bus
that conflicts with a pending processor coherent read request, it does not
forward the invalidate request to the processor since the targeted cache
line is absent from the processor cache. This scheme for conflict detection
on processor coherent read requests could reduce the number of external
intervention and invalidate requests issued to the processor. However,
since the intervention and invalidate requests that would otherwise be
issued to the processor cannot result in any state modification within the
processor (since the targeted cache line is not present in the cache), conflict
detection for processor coherent read requests is not necessary.
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