Chapter 1
30 MIPS R4000 Microprocessor User's Manual
Floating-Point Unit (FPU), CP1
The MIPS floating-point unit (FPU) is designated CP1; the FPU extends
the CPU instruction set to perform arithmetic operations on floating-point
values. The FPU, with associated system software, fully conforms to the
requirements of ANSI/IEEE Standard 754–1985, IEEE Standard for Binary
Floating-Point Arithmetic.
The FPU features include:
• Full 64-bit Operation. The FPU can contain either 16 or 32
64-bit registers to hold single-precision or double-precision
values. The FPU also includes a 32-bit Status/Control register
that provides access to all IEEE-Standard exception handling
capabilities.
• Load and Store Instruction Set. Like the CPU, the FPU uses a
load- and store-based instruction set. Floating-point operations
are started in a single cycle and their execution overlaps other
fixed-point or floating-point operations.
• Tightly-coupled Coprocessor Interface. The FPU is on the
CPU chip, and appears to the programmer as a simple
extension of the CPU (accessed as CP1). Together, the CPU and
FPU form a tightly-coupled unit with a seamless integration of
floating-point and fixed-point instruction sets. Since each unit
receives and executes instructions in parallel, some floating-
point instructions can execute at the same rate (two
instructions per cycle) as fixed-point instructions.
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