MIPS R4000 Microprocessor User's Manual 95
Memory Management
Virtual-to-Physical Address Translation Process
During virtual-to-physical address translation, the CPU compares the
8-bit ASID (if the Global bit, G, is not set) of the virtual address to the ASID
of the TLB entry to see if there is a match. One of the following
comparisons are also made:
• In 32-bit mode, the highest 7-to-19 bits (depending upon the
page size) of the virtual address are compared to the contents
of the TLB virtual page number.
• In 64-bit mode, the highest 15-to-27 bits (depending upon the
page size) of the virtual address are compared to the contents
of the TLB virtual page number.
If a TLB entry matches, the physical address and access control bits (C, D,
and V) are retrieved from the matching TLB entry. While the V bit of the
entry must be set for a valid translation to take place, it is not involved in
the determination of a matching TLB entry.
Figure 4-20 illustrates the TLB address translation process.
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