Chapter 5
100 MIPS R4000 Microprocessor User's Manual
5.1 How Exception Processing Works
The processor receives exceptions from a number of sources, including
translation lookaside buffer (TLB) misses, arithmetic overflows, I/O
interrupts, and system calls. When the CPU detects one of these
exceptions, the normal sequence of instruction execution is suspended
and the processor enters Kernel mode (see Chapter 4 for a description of
system operating modes).
The processor then disables interrupts and forces execution of a software
exception processor (called a handler) located at a fixed address. The
handler saves the context of the processor, including the contents of the
program counter, the current operating mode (User or Supervisor), and
the status of the interrupts (enabled or disabled). This context is saved so
it can be restored when the exception has been serviced.
When an exception occurs, the CPU loads the Exception Program Counter
(EPC) register with a location where execution can restart after the
exception has been serviced. The restart location in the EPC register is the
address of the instruction that caused the exception or, if the instruction
was executing in a branch delay slot, the address of the branch instruction
immediately preceding the delay slot.
The registers described later in the chapter assist in this exception
processing by retaining address, cause and status information.
For a description of the exception handling process, see the description of
the individual exception contained in this chapter, or the flowcharts at the
end of this chapter.
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