MIPS R4000 Microprocessor User's Manual 265
Cache Organization, Operation, and Coherency
Uncached
Lines within an uncached page are never in a cache. When a page has the
uncached coherency attribute, the processor issues a doubleword, partial-
doubleword, word, or partial-word read or write request directly to main
memory (bypassing the cache) for any load or store to a location within
that page.
Noncoherent
Lines with a noncoherent attribute can reside in a cache; a load or store miss
causes the processor to issue a noncoherent block read request to a
location within the cached page.
Sharable
Lines with a sharable attribute must be in a multiprocessor environment
(using the R4000MC), since shared lines can be in more than one cache at
a time. When the coherency attribute is sharable, the processor operates as
follows:
• a coherent block read request is issued for a load miss to a
location within the page, or
• a coherent block read request that requests exclusivity is issued
for a store miss to a location within the page.
In most systems, coherent read requests require snoops or directory
checks, and noncoherent read requests do not.
†
Cache lines within the
page are managed with a write invalidate protocol; that is, the processor
issues an invalidate request on a store hit to a shared cache line.
Update
Lines with an update coherency attribute must be in a multiprocessor
environment and can reside in more than one cache at a time. When the
coherency attribute is update, the processor issues a coherent block read
request for a load or store miss to a location within the page. Cache lines
within the page are managed with a write update protocol; that is, the
processor issues an update request on a store hit to a shared cache line.
† A coherent read that requests exclusivity implies that the processor functions most
efficiently if the requested cache line is returned to it in an exclusive state, but the
processor still performs correctly if the cache line is returned in a shared state.
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