Mips Technologies R4000 - Instruction Scheduling Constraints

To Next Page

To Previous Page

Chapter 6

176 MIPS R4000 Microprocessor User's Manual

Instruction Scheduling Constraints

The FPU resource scheduler is kept from issuing instructions to the FPU

op units (adder, multiplier, and divider) by the limitations in their micro-

architectures. If any of the following constraints are violated, the op unit

assumes the outstanding instruction in its pipe is discarded, and then

continues operation on the most recently issued instruction.

FPU Divider Constraints

The FPU divider can handle only one non-overlapped division instruction

in its pipe at any one time.

FPU Multiplier Constraints

The FPU multiplier allows up to two pipelined MUL.[S,D] instructions to

be processed as long as the following constraints are met:

• Two idle cycles are required after a MUL.S instruction (as

shown in Figure 6-11).

• Three idle cycles are required after MUL.D instruction (as

shown in Figure 6-12).

These figures are not meant to imply that back-to-back multiplications are

allowed. Rather, as shown in Figure 6-11, instructions I2 and I3 are illegal

and I5, I6, I7, and I8 are successive stages of I4, referenced to I1.

Figure 6-12 is similar, in that I6, I7, and I8 are successive stages of I5.

Figure 6-11 MUL.S Instruction Scheduling in the FPU Multiplier

UMMMNN/A

UMMMMN N/A R

MUL.S

MUL.[S.D]

Yes

UMMMMN N/A R

Yes

MUL.[S.D]

Legal to Issue?

– – – – – – – – – – – – – – – – –

– – – – – – – – – – – – – –

– – – – – –

– – – – – – – – –

– – – – – – – – – – –

– – –