Mips Technologies R4000 - Cross-Coupled Checking Configuration

MIPS R4000 Microprocessor User's Manual 433
Error Checking and Correcting
Cross-Coupled Checking Configuration
In the Cross-Coupled Checking configuration, one of the R4400 processors
drives the data bus pins and is labelled the System Interface Master (mode
bits 42 and 18 = 10
2
). The other R4400 processor drives the ECC or parity
check pins on the same bus and is labelled the Secondary Cache Master
(mode bits 42 and 18 = 01
2
). This is shown in Figure 16-6.
Both processors monitor the buses and indicate a miscomparison by
asserting their respective Fault* signals. The Fault* signal indicates error
conditions not specifically covered by R4400 processor exceptions.
†
Figure 16-6 Cross-Coupled Configuration of Master/Checker Mode
† This includes such errors as an input parity error at SysCmd.
Fault*
External
Agent
R4400
SI Master
Secondary cache
SC Master
System Interface bus
=?
=?
=?
=?
=?
Secondary cache bus
Data Chk/
SCAddress
Maintenance
Processor
R4400
SCData/
Data Chk/
Tag Chk
SCData/
SCTag
Address
Fault*
Fault*
SysAD/
SysADC/
Tag Chk
SCTag
Data Chk/
Tag Chk
SysCmd
SysCmdP
SysAD/
SysCmd
SCData/
SCTag
SysAD/
SysCmd
SysADC/
SysCmdP
SysADC/
SysCmdP