Mips Technologies R4000 - Status Register Modes and Access States

MIPS R4000 Microprocessor User's Manual 109
CPU Exception Processing
Status Register Modes and Access States
Fields of the Status register set the modes and access states described in the
sections that follow.
Interrupt Enable: Interrupts are enabled when all of the following
conditions are true:
• IE = 1
• EXL = 0
• ERL = 0
If these conditions are met, the settings of the IM bits enable the interrupt.
Operating Modes: The following CPU Status register bit settings are
required for User, Kernel, and Supervisor modes (see Chapter 4 for more
information about operating modes).
• The processor is in User mode when KSU = 10
2
, EXL = 0, and
ERL = 0.
• The processor is in Supervisor mode when KSU = 01
2
, EXL = 0,
and ERL = 0.
• The processor is in Kernel mode when KSU = 00
2
, or EXL = 1,
or ERL = 1.
32- and 64-bit Modes: The following CPU Status register bit settings select
32- or 64-bit operation for User, Kernel, and Supervisor operating modes.
Enabling 64-bit operation permits the execution of 64-bit opcodes and
translation of 64-bit addresses. 64-bit operation for User, Kernel and
Supervisor modes can be set independently.
• 64-bit addressing for Kernel mode is enabled when KX = 1.
64-bit operations are always valid in Kernel mode.
• 64-bit addressing and operations are enabled for Supervisor
mode when SX = 1.
• 64-bit addressing and operations are enabled for User mode
when UX = 1.
Kernel Address Space Accesses: Access to the kernel address space is
allowed when the processor is in Kernel mode.
Supervisor Address Space Accesses: Access to the supervisor address
space is allowed when the processor is in Kernel or Supervisor mode, as
described above in the section above titled, Operating Modes.