MIPS R4000 Microprocessor User's Manual 235
Clock Interface
10.5 Connecting Clocks to a System without Phase Locking
When the R4000 processor is used in a system in which the external agent
cannot lock its phase to a common MasterClock, the output clocks RClock
and TClock can clock the remainder of the system. Two clocking
methodologies are described in this section: connecting to a gate-array
device or connecting to discrete CMOS logic devices.
Connecting to a Gate-Array Device
When connecting to a gate-array device, both RClock and TClock are
used within the gate-array. The gate array internally buffers RClock and
uses this buffered version to clock registers that sample processor outputs.
These sampling registers should be immediately followed by staging
registers clocked by an internally buffered version of TClock. This
buffered version of TClock should be the global system clock for the logic
inside the gate array and the clock for all registers that drive processor
inputs. Figure 10-6 is a block diagram of this circuit.
Staging registers place a constraint on the sum of the clock-to-Q delay of
the sample registers and the setup time of the staging registers inside the
gate arrays, as shown in the following equation:
Figure 10-6 is a block diagram of a system without phase lock, using the
R4000 processor with an external agent implemented as a gate array.
Clock-to-Q Delay + Setup of Staging Register
– (Maximum Clock Jitter for RClock)
– (Maximum Delay Mismatch for Internal Clock 0.25 (RClock period)
Buffers on RClock and TClock)
To Next Page
Loading...