Mips Technologies R4000 - Page 266

Mips Technologies R4000

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Chapter 10

236 MIPS R4000 Microprocessor User's Manual

Figure 10-6 Gate-Array System without Phase Lock, using the R4000 Processor

MasterClock

R4000

TClock

RClock

SysAD

SysCmd

MasterClock

SyncOut

SyncIn

CE

CE

Gate

Array

Sampling

Register

Staging

Register

Sampling

Register

Staging

Register

Table of Contents

Default Chapter14
- Table of Contents14
Introduction32
- Benefits of RISC Design32
- Compatibility36
- Processor General Features36
- R4000 Processor Configurations37
- R4400 Processor Enhancements37
- R4000 Processor39
CPU Instruction Set Summary65
- CPU Instruction Formats66
The CPU Pipeline73
- CPU Pipeline Operation74
- CPU Pipeline Stages75
- Branch Delay78
- Load Delay78
- Interlock and Exception Handling79
- R4400 Processor Uncached Store Buffer89
- Memory Management91
Memory Management92
- Translation Lookaside Buffer (TLB)92
  - Hits and Misses92
  - Multiple Matches92
- Address Spaces93
- System Control Coprocessor110
CPU Exception Processing130
- How Exception Processing Works130
- Exception Processing Registers131
Output Buffer ∆I/∆T Control Mechanism137
- Mode Bits137
- Processor Exceptions149
- Exception Handling and Servicing Flowcharts174
Floating-Point Unit182
- Overview182
- FPU Features183
- FPU Programming Model184
- Floating-Point Formats194
- Binary Fixed-Point Format196
- Floating-Point Instruction Set Overview197
- FPU Instruction Pipeline Overview202
Floating-Point Exceptions217
- Exception Types218
- Exception Trap Processing219
- Flags220
- FPU Exceptions222
- Saving and Restoring State227
- Trap Handlers for IEEE Standard 754 Exceptions228
R4000 Processor Signal Descriptions229
- System Interface Signals231
- Clock/Control Interface Signals233
- Secondary Cache Interface Signals235
- Interrupt Interface Signals237
- JTAG Interface Signals237
- Initialization Interface Signals238
- Signal Summary239
Initialization Interface243
- Functional Overview244
- Reset Signal Description245
- Initialization Sequence248
- Warm Reset251
Subblock Ordering252
- Sequential Ordering252
Clock Interface257
- Signal Terminology258
- Basic System Clocks259
- System Timing Parameters263
- Connecting Clocks to a Phase-Locked System264
- Connecting Clocks to a System Without Phase Locking265
  - Connecting to a Gate-Array Device265
  - Connecting to a CMOS Logic System268
- Processor Status Outputs271
Cache Organization, Operation, and Coherency274
- Memory Organization274
- Overview of Cache Operations275
- R4000 Cache Description276
- Cache States285
- Cache Line Ownership288
- Cache Write Policy289
- Cache State Transition Diagrams290
- Cache Coherency Overview294
- Maintaining Coherency on Loads and Stores299
- Manipulation of the Cache by an External Agent300
- Coherency Conflicts301
- R4000 Processor Synchronization Support316
System Interface324
- Terminology324
- System Interface Description324
  - Interface Buses325
    - Address and Data Cycles326
    - Issue Cycles326
  - Handshake Signals328
- System Interface Protocols329
- Processor and External Requests332
- Handling Requests348
- Processor and External Request Protocols359
  - Processor Request Protocols360
  - External Request Protocols371
- Data Rate Control386
- System Interface Cycle Time391
- System Interface Commands and Data Identifiers394
Secondary Cache Interface409
- Data Transfer Rates410
- Duplicating Signals410
- Accessing a Split Secondary Cache411
- Scdchk Bus411
- SCTAG Bus411
- Operation of the Secondary Cache Interface412
  - Read Cycles413
  - Write Cycles415
JTAG Interface419
- What Boundary Scanning Is420
- Signal Summary421
- JTAG Controller and Registers422
- Implementation-Specific Details430
R4000 Processor Interrupts431
- Hardware Interrupts432
- Nonmaskable Interrupt (NMI)432
- Asserting Interrupts432
Error Checking and Correcting438
- Error Checking in the Processor438
- R4400 Master/Checker Mode460
- Delay Times720
- Cpu Board721
R4000 Pinouts732
- Pinout of R4000PC732
- Pinout of R4000MC/SC Package Pinout735