Mips Technologies R4000 - Operation of the Secondary Cache Interface

Chapter 13
382 MIPS R4000 Microprocessor User's Manual
13.6 Operation of the Secondary Cache Interface
The secondary cache can be configured for various clock rates and static
RAM speeds. All configurable parameters are specified in multiples of
PClock, which runs at twice the frequency of the external system clock,
MasterClock.
During boot time, secondary cache timing parameters are programmed
through the boot-time mode bits, as described in Chapter 9. Table 13-1
lists the secondary cache timing parameters. The following sections
describe secondary cache read and write cycles.
Table 13-1 Secondary Cache Timing Parameters
Symbol Number of Cycles
t
Rd1Cyc
4-15 PCycles
t
Rd2Cyc
2-15 PCycles
t
Dis
2-7 PCycles
t
Wr1Dly
1-3 PCycles
t
Wr2Dly
1-3 PCycles
t
WrRC
0-1 PCycles
t
WrSUp
3-15 PCycles