Mips Technologies R4000 - Aborting an Instruction Subsequent to an Interlock

MIPS R4000 Microprocessor User's Manual 55
The CPU Pipeline
Aborting an Instruction Subsequent to an Interlock
The interaction between an integer overflow and an instruction cache miss
is an example of an interlock being serviced for an instruction that is
subsequently aborted.
In this case, pipelining the overflow exception handling into the DF stage
allows an instruction cache miss to occur on the next immediate
instruction. Figure 3-8 illustrates this; aborted instructions are indicated
with an asterisk (*).
Figure 3-8 Instruction Cache Miss
Even though the line brought in by the instruction cache could have been
replaced by a line of the exception handler, no performance loss occurs,
since the instruction cache miss would have been serviced anyway, after
returning from the exception handler. Handling of the exception is done
in this fashion because the frequency of an exception occurring is, by
definition, relatively low.
Run Run Run Run Stl Stl Stl Stl Stl Run Run Run Run Run Run Run
Rst2 Rst1
IF IS RF EX DF DS TC WB*
IF IS RF IF IS RF EX DF DS TC WB*
IF IS IF IS RF EX DF DS TC WB*
IF IF IS RF EX DF DS TC WB*
Cycle
Restart
Stall
ALU
OVF
ICM
InstrCacheMiss