Chapter 11
272 MIPS R4000 Microprocessor User's Manual
The R4000MC processor issues the following processor coherency
requests:
• processor coherent read requests
• processor invalidate requests
• processor update requests
The R4000MC processor accepts the following external coherency
requests:
• external invalidate requests
• external update requests
• external snoop requests
• external intervention requests
How Coherency Conflicts Arise
Because of the overlapped nature of the system interface, it is possible for
an external coherency request to target the same cache physical address as
a pending processor read request, an unacknowledged processor
invalidate, or an update request. The processor does not contain the
comparison mechanism necessary to detect such conflicts; instead, it uses
the secondary cache as a point of reference to determine suitable
coherency actions, and only checks the state of the secondary cache at
specific times.
Processor Coherent Read Requests
When the processor wants to service either a store or load cache miss for a
page that has a coherent page attribute in the TLB (meaning the data
passed back and forth should follow a defined multiprocessor coherency
scheme), a coherent read request is used.
Conflicting external coherency requests cannot affect the behavior of the
processor for pending processor coherent read requests. The processor
only issues read requests for a range of physical addresses not currently in
the cache; consequently, an external coherency request that targets the
same physical address range will not find this physical address range in
the cache. In such a case, the processor simply discards any external
coherency requests that conflict with a pending processor coherent read
request.
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