Chapter 12
330 MIPS R4000 Microprocessor User's Manual
Processor Request Protocols
Processor request protocols described in this section include:
• read
• write
• invalidate and update
• null write
• cluster
NOTE: In the timing diagrams, the two closely spaced, wavy vertical
lines (such as those shown in Figure 12-16) indicate one or more iden-
tical cycles which are not illustrated due to space constraints.
Figure 12-16 Symbol for Undocumented Cycles
Processor Read Request Protocol
The following sequence describes the protocol for a processor read request
(the numbered steps below correspond to Figures 12-17 and 12-18).
1. RdRdy* is asserted low, indicating the external agent is ready to
accept a read request.
2. With the System interface in master state, a processor read request is
issued by driving a read command on the SysCmd bus and a read
address on the SysAD bus.
3. At the same time, the processor asserts ValidOut* for one cycle,
indicating valid data is present on the SysCmd and the SysAD buses.
NOTE: Only one processor read request can be pending at a time.
4. The processor makes an uncompelled change to slave state either at
the issue cycle of the read request, or sometime after the issue cycle of
the read request by asserting the Release* signal for one cycle.
To Next Page
Loading...