MIPS R4000 Microprocessor User's Manual 333
System Interface
Processor Write Request Protocol
Processor write requests are issued using one of two protocols.
• Doubleword, partial doubleword, word, or partial word writes
use a word
†
write request protocol.
• Block writes use a block write request protocol.
Processor doubleword write requests are issued with the System interface
in master state, as described below in the steps below; Figure 12-19 shows
a processor noncoherent single word write request cycle.
1. A processor single word write request is issued by driving a write
command on the SysCmd bus and a write address on the SysAD bus.
2. The processor asserts ValidOut*.
3. The processor drives a data identifier on the SysCmd bus and data on
the SysAD bus.
4. The data identifier associated with the data cycle must contain a last
data cycle indication. At the end of the cycle, ValidOut* is deasserted.
NOTE: Timings for the SysADC and SysCmdP buses are the same as
those of the SysAD and SysCmd buses, respectively.
Figure 12-19 Processor Noncoherent Single Word Write Request Protocol
† Called word to distinguish it from block request protocol. Data transferred can actually be
doubleword, partial doubleword, word, or partial word.
SCycle
1 2 3 4 5 6 7 8 9 10 11 12
SClock
SysAD Bus
Addr Data0
SysCmd Bus
Write NEOD
ValidOut*
ValidIn*
RdRdy*
WrRdy*
Release*
4
2
1
Master
3
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