Chapter 12
308 MIPS R4000 Microprocessor User's Manual
Processor Invalidate Request
An invalidate request notifies all processors that the specified cache line
must be marked invalid in all caches in the system. Invalidate requests can
only be used in a multiprocessing system.
When a processor issues an invalidate request, the specified resource is
accessed and the line is marked invalid. (Processor invalidate requests are
described in this section; external invalidate requests are described in
External Requests, later on in this chapter.)
A processor invalidate request requires a completion acknowledge by
either the invalidate acknowledge signal IvdAck* or the invalidate error
signal IvdErr*, unless the invalidate is canceled by the external agent. A
processor invalidate request that has been submitted, but for which the
processor has not yet received an acknowledge or a cancellation, is said to
be unacknowledged. When the processor invalidate request fails (IvdErr* is
asserted), the issuing processor takes a bus error on the store instruction
that generated the failed request. Figure 12-10 shows a sample processor
invalidate/update request cycle.
Invalidate cancellation is signaled to the processor during external
invalidate, update, snoop, and intervention requests; IvdErr* signals a
processor invalidate request has failed.
A completion acknowledge for processor invalidate requests is signaled
through the System interface on dedicated pins, and this acknowledgment
can occur in parallel with processor and external requests.
State changes in the external system are not instantaneously reflected in
the caches of every processor, which means an external agent can discover
that a processor request for an invalidate cannot be completed. For
example, a processor store can hit on a shared cache line and issue an
invalidate to the external agent. However, before the external agent can
transmit the invalidate to the rest of the system another invalidate for the
same cache line can be received by the external agent. If this occurs, the
processor cache does not reflect the current state of the system and the
processor invalidate must not be transmitted to the system; instead, the
external agent must cancel the processor unacknowledged invalidate.
Figure 12-9 shows this cancellation cycle.
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