Mips Technologies R4000 - Memory Management

MIPS R4000 Microprocessor User's Manual 61
Memory Management
4
The MIPS R4000 processor provides a full-featured memory management
unit (MMU) which uses an on-chip translation lookaside buffer (TLB) to
translate virtual addresses into physical addresses.
This chapter describes the processor virtual and physical address spaces,
the virtual-to-physical address translation, the operation of the TLB in
making these translations, and those System Control Coprocessor (CP0)
registers that provide the software interface to the TLB.