Chapter 1
32 MIPS R4000 Microprocessor User's Manual
Operating Modes
The R4000 processor has three operating modes:
• User mode
• Supervisor mode
• Kernel mode
The manner in which memory addresses are translated or mapped depends
on the operating mode of the CPU; this is described in Chapter 4.
Cache Memory Hierarchy
To achieve a high performance in uniprocessor and multiprocessor
systems, the R4000 processor supports a two-level cache memory
hierarchy that increases memory access bandwidth and reduces the
latency of load and store instructions. This hierarchy consists of on-chip
instruction and data caches, together with an optional external secondary
cache that varies in size from 128 Kbytes to 4 Mbytes.
The secondary cache is assumed to consist of one bank of industry-
standard static RAM (SRAM) with output enables, arranged as a
quadword (128-bit) data array, with a 25-bit-wide tag array. Check fields
are added to both data and tag arrays to improve data integrity.
The secondary cache can be configured as a joint cache, or split into
separate instruction and data caches. The maximum secondary cache size
is 4 Mbytes; the minimum secondary cache size is 128 Kbytes for a joint
cache, or 256 Kbytes total for split instruction/data caches. The secondary
cache is direct mapped, and is addressed with the lower part of the
physical address.
Primary and secondary caches are described in more detail in Chapter 11.
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