Mips Technologies R4000 - Write Cycles; 4-Word Write Cycle

MIPS R4000 Microprocessor User's Manual 385
Secondary Cache Interface
Write Cycles
There are two basic write cycles: a 4-word write cycle and an 8-word write
cycle. The secondary cache write cycle begins with the assertion of an
address onto the address pins.
This section describes both 4-word and 8-word write cycles, including
timing diagrams.
4-Word Write Cycle
A 4-word write cycle has three timing parameters:
t
Wr1Dly
delay from the assertion of the address to the
assertion of SCWR*
t
WrSUp
delay from assertion of the second data double-
word to the deassertion of SCWR*
t
WrRc
delay from the deassertion of SCWR* to the
beginning of the next cycle
The timing parameter t
WrRc
is 0 for most cache designs. Note that the
upper data doubleword and the lower data doubleword are normally
driven one cycle apart; this reduces the peak current consumption in the
output drivers.
Figure 13-4 illustrates the 4-word write cycle. Either the upper or lower
data doubleword can be driven first.