Mips Technologies R4000 - Basic System Clocks; Masterclock; Masterout; Syncin;Syncout

MIPS R4000 Microprocessor User's Manual 229
Clock Interface
10.2 Basic System Clocks
The various clock signals used in the R4000 processor are described below,
starting with MasterClock, upon which the processor bases all internal
and external clocking.
MasterClock
The processor bases all internal and external clocking on the single
MasterClock input signal. The processor generates the clock output
signal, MasterOut, at the same frequency as MasterClock and aligns
MasterOut with MasterClock, if SyncIn is connected to SyncOut.
MasterOut
The processor generates the clock output signal, MasterOut, at the same
frequency as MasterClock and aligns MasterOut with MasterClock, if
SyncIn is connected to SyncOut. MasterOut clocks external logic, such as
the reset logic.
SyncIn/SyncOut
The processor generates SyncOut at the same frequency as MasterClock
and aligns SyncIn with MasterClock.
SyncOut must be connected to SyncIn either directly, or through an
external buffer. The processor can compensate for both output driver and
input buffer delays (and, when necessary, delay caused by an external
buffer) when aligning SyncIn with MasterClock. Figure 10-7 gives an
illustration of SyncOut connected to SyncIn through an external buffer.
PClock
The processor generates an internal clock, PClock, at twice the frequency
of MasterClock and precisely aligns every other rising edge of PClock
with the rising edge of MasterClock.
All internal registers and latches use PClock.