Mips Technologies R4000 - SECDED ECC Code

MIPS R4000 Microprocessor User's Manual 379
Secondary Cache Interface
13
The R4000SC and R4000MC versions of the R4000 processor contain
interface signals for an optional external secondary cache. This interface
consists of:
• a 128-bit data bus
• a 25-bit tag bus
• an 18-bit address bus
• various static random access memory (SRAM) control signals.
The 128-bit-wide data bus minimizes the primary cache miss penalty, and
allows the use of standard low-cost SRAMs in the design of the secondary
cache.
The remainder of the System interface signals are described in Chapter 8.