Mips Technologies R4000 - System Timing Parameters; Alignment to Sclock; Alignment to Masterclock; Phase-Locked Loop (PLL)

MIPS R4000 Microprocessor User's Manual 233
Clock Interface
10.3 System Timing Parameters
As shown in Figures 10-3 and 10-4, data provided to the processor must be
stable a minimum of t
DS
nanoseconds (ns) before the rising edge of SClock
and be held valid for a minimum of t
DH
ns after the rising edge of SClock.
Alignment to SClock
Processor data becomes stable a minimum of t
DM
ns and a maximum of
t
DO
ns after the rising edge of SClock. This drive-time is the sum of the
maximum delay through the processor output drivers together with the
maximum clock-to-Q delay of the processor output registers.
Alignment to MasterClock
Certain processor inputs (specifically VCCOk, ColdReset*, and Reset*)
are sampled based on MasterClock, while others (specifically, Status(7:0))
are output based on MasterClock. The same setup, hold, and drive-off
parameters, t
DS
, t
DH
,t
DM
, and t
DO
, shown in Figures 10-3 and 10-4, apply
to these inputs and outputs, but they are measured by MasterClock
instead of SClock.
Phase-Locked Loop (PLL)
The processor aligns SyncOut, PClock, SClock, TClock, and RClock with
internal phase-locked loop (PLL) circuits that generate aligned clocks
based on SyncOut/SyncIn. By their nature, PLL circuits are only capable
of generating aligned clocks for MasterClock frequencies within a limited
range.
Clocks generated using PLL circuits contain some inherent inaccuracy, or
jitter; a clock aligned with MasterClock by the PLL can lead or trail
MasterClock by as much as the related maximum jitter allowed by the
individual vendor.