MIPS R4000 Microprocessor User's Manual 9
Introduction
1.6 R4000 Processor
This section describes the following:
• the 64-bit architecture of the R4000 processor
• the superpipeline design of the CPU instruction pipeline
(described in detail in Chapter 3)
• an overview of the System interface (described in detail in
Chapter 12)
• an overview of the CPU registers (detailed in Chapters 4 and 5)
and CPU instruction set (detailed in Chapter 2 and Appendix
A)
• data formats and byte ordering
• the System Control Coprocessor, CP0, and the floating-point
unit, CP1
• caches and memory, including a description of primary and
secondary caches, the memory management unit (MMU), the
translation lookaside buffer (TLB), and the Secondary Cache
interface (described in more detail in Chapters 4 and 11). The
Secondary Cache interface is detailed in Chapter 13.
64-bit Architecture
The natural mode of operation for the R4000 processor is as a 64-bit
microprocessor; however, 32-bit applications maintain compatibility even
when the processor operates as a 64-bit processor.
The R4000 processor provides the following:
• 64-bit on-chip floating-point unit (FPU)
• 64-bit integer arithmetic logic unit (ALU)
• 64-bit integer registers
• 64-bit virtual address space
• 64-bit system bus
Figure 1-1 is a block diagram of the R4000 processor internals.
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