MIPS R4000 Microprocessor User's Manual 431
Error Checking and Correcting
Connecting a System in Lock Step
By operating in lock step, a system with more than one R4400 processor
can be configured to improve data integrity. In such a configuration,
output signals and I/O buses used during output are connected in parallel
between the processors. One processor is defined at boot time as a bus
driver, and the remaining processor(s) is defined as a bus monitor.
Starting with the assertion of Reset*, all microprocessors must be
synchronous, and execute identical operations on a cycle-by-cycle basis.
The processor(s) designated as bus monitor compares the outputs and
buses at bus-cycle boundaries, and asserts the Fault*
†
signal on any
mismatch.
In a lock step operation, the following R4400 signal groups are connected
in parallel:
• System interface
• Secondary Cache interface (R4400SC and R4400MC only)
• Interrupt interface
The following signals are not connected in parallel:
• Initialization interface, ModeClock, ModeIn, and Reset*
signals
• JTAG interface signals, JTDO and JTMS
• all Clock/Control interface signals except VssP and VccP
The remaining processor signals can be connected either in parallel or
independently.
† Fault* is a non-persistent signal which is synchronous with the System interface. Fault*
signal timing is determined by the PClock-to-SClock divisor from boot-time mode bit
settings.
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